The present invention is directed, in general, to signal processing circuits and, more specifically, to a divider circuit, method of operation thereof and a phase-locked loop (PLL) circuit incorporating the same.
In modern digital electronic computers, cooperating sequential logic circuits performing routine operations, are each controlled by derivatives of a master, or reference, clock signal. These derivative clock signals are typically synchronized within the system to assist in optimizing computer functions, although they often do not arrive at their intended destinations in proper synchronism. Reasons for such skew in the derivative signals include, for example, variations in signal propagation delay for each destination. As a result, combining several complex sequential logic circuits within a system presents a challenge with respect to synchronizing the clock signals transmitted to the respective circuits therein.
As application specific integrated circuits (ASICs) such as high density programmable logic devices (PLDs) become available, on-chip clock distribution becomes more important to the integrity and performance of the designs implemented in these devices. Unfortunately, with the advent of ASCIs such as high-density PLDs, difficulties in managing clock delay and clock skew on these devices has become substantial. Many existing solutions for such problems, such as hardwired clock trees, are less effective for the applications found in today""s programmable logic market. As integration levels of microelectronic circuits and system complexity continue to increase, the routing or distribution of a master system clock has become even more critical. This challenge is especially exacerbated in view of ever increasing clock rates in today""s powerful microprocessors.
A common solution is the incorporation of a circuit having a phase-locked loop (PLL) architecture to assist in synchronizing clock signals in such devices. Because of the advantages, employing a voltage controlled oscillator (VCO) in a clock management circuit to create a PLL architecture has continued to gain popularity among device designers. Such ring oscillators generate an output clock signal from a comparison between the reference clock signal and a feedback signal derived from the output signal. By doing so, the PLL architecture provides feedback that is used to nullify clock distribution problems within the circuit. The difference between the two signals is used in a feedback control system to bring the signals into a substantially fixed phase relation.
Commonly, such PLL circuits are employed to also alter the frequency of the output signal, so-called xe2x80x9cfrequency synthesis.xe2x80x9d To provide frequency synthesis, one or both of the incoming signals are divided before being input to the VCO. Those skilled in the art understand that arriving at an output signal of a signal divider based on a factor of two is relatively simple. In such a case, a single divider may be used to divide the incoming feedback signal before being compared with the reference clock signal. For example, if the output signal of a divider circuit with a frequency of 10 MHz is desired from a feedback signal of 20 MHz, a single divider with a value of n=2 may be used to arrive at the desired output signal.
The difficulty in signal division increases when the output signal desired from the divider circuit cannot be derived as a factor of two (an even factor). For example, if an output signal with a frequency of 10 MHz is desired from a 150 MHz feedback signal, a divide factor of 15 must be created. Since 15 is not an even factor, a second divider circuit is typically used to divide the reference clock signal, while the first divider circuit is still used to divide the feedback signal. The two divided signals may then be combined to arrive at the desired odd-numbered frequency. In this example, the first divider circuit may use a divide factor of n=30, while the second divider circuit may use a divide factor of m=2 (both even factors), to arrive at an overall divide factor of n/m=30/2=15 (an odd factor).
Although quite common, the use of two dividers in prior art PLL circuits has disadvantages. More specifically, employing two dividers, for instance in an odd-factor signal divide, involves the use of extra logic devices, an inefficient use of circuit time and power. In addition, employing a second divider to modify the reference clock signal from its original state may result in excessive jitter in the circuit. Moreover, for programmable systems where the frequency of the output signal is selectable xe2x80x9con-the-flyxe2x80x9d, control logic configured to control both dividers needs to be included in the PLL circuit. Those skilled in the art understand the high cost often associated with such controllers, as well as the complex logic circuits required for two divide operations.
Accordingly, what is needed in the art is a divider circuit employable in a PLL environment that overcomes the deficiencies found in the prior art.
To address the above-discussed deficiencies of the prior art, the present invention provides a divider circuit that performs operations on an input signal, such as a clock signal. In one embodiment, the divider circuit includes a counting subcircuit configured to count rising and falling edges of the input signal. In addition, the divider circuit includes a signal generator configured to provide an output signal by performing an operation on the count of the rising and falling edges of the input signal based on a divisor control signal.
The present invention also provides a method of operating a divider circuit. In one embodiment, the method includes counting rising and falling edges of an input signal, and providing an output signal by performing an operation on the count of the rising and falling edges of the input signal based on a divisor control signal.
In addition, the present invention provides a phase-locked loop (PLL) circuit. In one embodiment, the PLL circuit includes a comparator circuit configured to compare a phase of a feedback signal to a phase of an input signal of the PLL circuit and generate charge and discharge signals. The PLL circuit further includes a charge pump configured to generate a charge current as a function of the charge and discharge signals, as well as a filter configured to generate a control signal as a function of the charge and discharge signals. Also, the PLL circuit includes an oscillator configured to generate an output clock signal as a function of the control signal. The PLL circuit still further includes a divider circuit having a counting subcircuit configured to count rising and falling edges of the output clock signal, and a signal generator configured to provide the feedback signal by performing an operation on the count of the rising and falling edges of the output clock signal based on a divisor control signal.
The foregoing has outlined, rather broadly, preferred and alternative features of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.